The impact of the subthreshold leakage current on the circuit performance should be considered seriously as device dimension have scaled down to deep submicron level in CMOS technology. This is a significant problem in memory structures using precharging circuitry which frequently require discharging of the bitlines to allow bit sensing in memories.
FIG. 1 illustrates the schematic diagram for a conventional memory cell that operates as a single storage unit in a larger memory structure. One problem with such memory cells is the leakage current through multiple read transistors 30 coupled to a shared bitline 14 which can result in erroneous read operation. Increased leakage current severely affects the performance of the memory circuits (e.g., register files). Further, the problem is increased by noise on the read signal line due to coupling noise.
One way to reduce the leakage current is utilization of high threshold voltage (VT) devices. However, such devices exhibit reduced performance in terms of device speed and area. In addition, manufacturing costs are increased in high VT devices due to the additional silicon layers required in such devices.
To overcome this problem, FIG. 2 illustrates memory circuits according to U.S. Pat. No. 6,320,795. The patent discloses a register file cell 40 which is capable of reducing leakage current and is less likely to require a larger keeper transistor 26 to prevent erroneous reads. Memory cell 40 includes a pull-down transistor (MPD) 42, a static logic gate 44, and a storage cell 46. Pull-down transistor 42 is operative for discharging the bitline 14 to the ground 36 when a predetermined control indication is received at the input terminal thereof from the logic gate 44. In this embodiment, an N-channel IGFET device is used as the pull-down transistor 42 and therefore, the predetermined control indication is a logic high value applied to the gate terminal of pull-down transistor 42.
Logic gate 44 acts to buffer the input of the pull-down transistor 42 from the noise commonly associated with the read signal. Logic gate 44 includes two input terminals 48 and 50.
When the read signal is logic low and the data stored in the register file cell is logic high, logic gate 44 (NOR gate) outputs a logic high value to the gate terminal of pull-down transistor 42. As a result, pull-down transistor 42 discharges bitline 42 to ground 36. When stored data value in cell is logic low and when the read signal is logic low, the output of logic gate 44 is logic low which results in pull-down transistor 42 to be turned off and hence, bitline 14 is not discharged. The output of the logic gate 44 is logic low when the active low read signal is logic high, regardless of the data bit value stored in cell 46.
Thus the goal is to isolate pull-down transistor 42 from the read noise associated with the read signal. Although the application of a static logic gate helps to reduce such leakage current to a significant level in such circuits, this approach is effective for reducing the leakage currents generated only due to the noise voltages on the input terminal of pull-down transistor 42. The technique does not have significant impact on the leakage currents typically associated with low VT scaled devices.
FIG. 3 shows a schematic diagram illustrating a register file cell 60 with another embodiment. Memory cell 60 includes a pull-down transistor 62 (MPD), logic gate 64, a storage cell 66, a bias device 72 and a read transistor 74 (MREAD). Logic gate 64 of memory cell 60 provides isolation between a possibly noisy read signal and the input terminal of pull-down transistor 62, in the same way as in previous case. In addition, bias device 72 is operative for applying a bias voltage to pull-down transistor 62 during appropriate periods and thereby reduces the level of the current leakage through the device during those periods. Thus memory cell 60 can be implemented using low VT transistors to achieve high performance operation while still maintaining high robustness.
When the read signal is logic high, a read transistor 74 couples the second output terminal of pull-down transistor 62 to ground 36. Therefore a logic low voltage is present at the second input 70 of logic gate 64. During a read operation, the output of logic gate 64 is logic high when the data bit stored within cell 66 is logic low. Under this condition, pull-down transistor 62 is turned on and bitline 14 is discharged to the ground 36 through read transistor 74. When the data bit stored within cell 66 is logic high, the output of logic gate 64 is low and pull-down transistor 62 remains off.
When the read signal is logic high (i.e., a read operation is being performed for cell 60), bias device 72 (P-channel IGFET) is off and has substantially no effect on the circuit. When the read signal is logic low (i.e., a read operation is not being performed for cell 60), bias device 72 couples the supply terminal 18 to the second output terminal of pull-down transistor 62. This places a logic high voltage on the second input 70 of logic gate 64, which forces the output of the logic gate to a logic low value. Therefore a negative voltage exists from the input terminal of pull-down transistor 62 to the second output terminal of pull-down transistor 62. As transistor 62 is an N-channel IGFET device, the negative voltage from the input terminal (the gate) of pull-down transistor 62 to the second output terminal ( the source) of pull-down transistor 62 reduces the leakage current through pull-down transistor 62 to negligible levels. When the read signal again switches to a logic high value, the bias voltage is removed from pull-down transistor 62 and a read operation takes place.
As described in the prior art, such an embodiment is capable of reducing leakage current through pull-down transistor 62 due to the effect of read noise associated with read signal on the input of pull-down transistor 62. This helps to reduce the leakage level through pull-down transistor 62 due to generation of a negative voltage from the input terminal (i.e., the gate terminal) of pull-down transistor 62 to the second output terminal (i.e., the source terminal) of pull-down transistor 62.
The drawback of such an arrangement is its inability to check the leakage current through pull-down transistor 74. Also the presence of bias transistor X raises the potential of intermediate node 80 near to supply voltage whenever read signal is low (i.e., when a read operation is not being performed). This technique appears to be unable to reduce the leakage current to the same order at a very low potential of intermediate node. In such memory circuit arrangement, significant leakage current is produced because of low VT pull-down devices 107 and 117 used to maintain high performance. Hence, the goal of the bias device is to reduce leakage through pull-down transistor 62 during some or all of the non-read period associated with a register file cell.